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| author | Lei Huang <lei@ca.ibm.com> | 2018-05-24 03:20:28 +0000 |
|---|---|---|
| committer | Lei Huang <lei@ca.ibm.com> | 2018-05-24 03:20:28 +0000 |
| commit | f4ec67822fb6dd96bb9959d84178d220833325c2 (patch) | |
| tree | 1b8534c9ab380c580259fb27d96731333dfe15e2 /llvm/lib/Target/PowerPC | |
| parent | 4d53b744ca0e8f7efa43da5b43ed42120a3b32d9 (diff) | |
| download | bcm5719-llvm-f4ec67822fb6dd96bb9959d84178d220833325c2.tar.gz bcm5719-llvm-f4ec67822fb6dd96bb9959d84178d220833325c2.zip | |
[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo
instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post
RA based on the register pressure. To avoid ambiguity, we need to remove the
select pattern for LXSDX, same as what was done for LXSD. STXSDX also have
the same issue.
Patch by Qing Shan Zhang (steven.zhang).
Differential Revision: https://reviews.llvm.org/D47178
llvm-svn: 333150
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 71f21346434..85eb6e852e1 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -129,7 +129,7 @@ let Uses = [RM] in { def LXSDX : XX1Form_memOp<31, 588, (outs vsfrc:$XT), (ins memrr:$src), "lxsdx $XT, $src", IIC_LdStLFD, - [(set f64:$XT, (load xoaddr:$src))]>; + []>; // Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later let isPseudo = 1, CodeSize = 3 in @@ -160,7 +160,7 @@ let Uses = [RM] in { def STXSDX : XX1Form_memOp<31, 716, (outs), (ins vsfrc:$XT, memrr:$dst), "stxsdx $XT, $dst", IIC_LdStSTFD, - [(store f64:$XT, xoaddr:$dst)]>; + []>; // Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later let isPseudo = 1, CodeSize = 3 in |

