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authorBenjamin Kramer <benny.kra@googlemail.com>2014-05-19 13:12:38 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2014-05-19 13:12:38 +0000
commitf3ad23551ddf178496892c0e42d6df380ec13c89 (patch)
treec5d11954de565bc87ff68df835d5f322c20ff295 /llvm/lib/Target/PowerPC
parenta3afc69b949768a3aa01865132d9e5bf22a7fe2d (diff)
downloadbcm5719-llvm-f3ad23551ddf178496892c0e42d6df380ec13c89.tar.gz
bcm5719-llvm-f3ad23551ddf178496892c0e42d6df380ec13c89.zip
SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bswap not.
- On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index a0b3e467d20..04bd43547c7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -460,6 +460,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::SDIVREM, VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
+ setOperationAction(ISD::BSWAP, VT, Expand);
setOperationAction(ISD::CTPOP, VT, Expand);
setOperationAction(ISD::CTLZ, VT, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
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