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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-11-11 21:42:01 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-11-11 21:42:01 +0000 |
| commit | ec4b0c360f8e0e3870c41dab4894bc23c06843c2 (patch) | |
| tree | 3f8373d68e3b26bec00c43b250f0b9cf760aaabd /llvm/lib/Target/PowerPC | |
| parent | a0fb81fe37d5046f9c423675368790e43d1aa09a (diff) | |
| download | bcm5719-llvm-ec4b0c360f8e0e3870c41dab4894bc23c06843c2.tar.gz bcm5719-llvm-ec4b0c360f8e0e3870c41dab4894bc23c06843c2.zip | |
[PowerPC] Add remaining vector permute builtins in altivec.h - LLVM portion
This patch corresponds to review:
https://reviews.llvm.org/D26480
Adds all the intrinsics used for various permute builtins that will
be added to altivec.h.
llvm-svn: 286638
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 24 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrVSX.td | 4 |
2 files changed, 23 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index a81fd5cedd6..f9a500bea17 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -1337,10 +1337,26 @@ class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern> !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP, pattern>; // Vector Rotate Left Mask/Mask-Insert -def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", []>; -def VRLWMI : VX1_VT5_VA5_VB5<133, "vrlwmi", []>; -def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>; -def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>; +def VRLWNM : VX1_VT5_VA5_VB5<389, "vrlwnm", + [(set v4i32:$vD, + (int_ppc_altivec_vrlwnm v4i32:$vA, + v4i32:$vB))]>; +def VRLWMI : VXForm_1<133, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), + "vrlwmi $vD, $vA, $vB", IIC_VecFP, + [(set v4i32:$vD, + (int_ppc_altivec_vrlwmi v4i32:$vA, v4i32:$vB, + v4i32:$vDi))]>, + RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; +def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", + [(set v2i64:$vD, + (int_ppc_altivec_vrldnm v2i64:$vA, + v2i64:$vB))]>; +def VRLDMI : VXForm_1<197, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vDi), + "vrldmi $vD, $vA, $vB", IIC_VecFP, + [(set v2i64:$vD, + (int_ppc_altivec_vrldmi v2i64:$vA, v2i64:$vB, + v2i64:$vDi))]>, + RegConstraint<"$vDi = $vD">, NoEncode<"$vDi">; // Vector Shift Left/Right def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 4e7e921c0b6..e9a06f3a381 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -2144,7 +2144,9 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in { // Vector HP -> SP def XVCVHPSP : XX2_XT6_XO5_XB6<60, 24, 475, "xvcvhpsp", vsrc, []>; - def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, []>; + def XVCVSPHP : XX2_XT6_XO5_XB6<60, 25, 475, "xvcvsphp", vsrc, + [(set v4f32:$XT, + (int_ppc_vsx_xvcvsphp v4f32:$XB))]>; class Z23_VT5_R1_VB5_RMC2_EX1<bits<6> opcode, bits<8> xo, bit ex, string opc, list<dag> pattern> |
