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| author | Peter Collingbourne <peter@pcc.me.uk> | 2018-05-18 19:46:24 +0000 |
|---|---|---|
| committer | Peter Collingbourne <peter@pcc.me.uk> | 2018-05-18 19:46:24 +0000 |
| commit | e3f652973e6e4fb7074b0bdc2291493e6cb8fae5 (patch) | |
| tree | 4fba9f86235380483550bf1268b185f9aa2865f5 /llvm/lib/Target/PowerPC | |
| parent | 1fa76cc3ea1f3361dd4e6091ac6a5c0e833de6a4 (diff) | |
| download | bcm5719-llvm-e3f652973e6e4fb7074b0bdc2291493e6cb8fae5.tar.gz bcm5719-llvm-e3f652973e6e4fb7074b0bdc2291493e6cb8fae5.zip | |
Support: Simplify endian stream interface. NFCI.
Provide some free functions to reduce verbosity of endian-writing
a single value, and replace the endianness template parameter with
a field.
Part of PR37466.
Differential Revision: https://reviews.llvm.org/D47032
llvm-svn: 332757
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp | 15 |
1 files changed, 4 insertions, 11 deletions
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp index 92c8c224b71..2b948ca6002 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp @@ -122,25 +122,18 @@ public: // Output the constant in big/little endian byte order. unsigned Size = Desc.getSize(); + support::endianness E = IsLittleEndian ? support::little : support::big; switch (Size) { case 0: break; case 4: - if (IsLittleEndian) { - support::endian::Writer<support::little>(OS).write<uint32_t>(Bits); - } else { - support::endian::Writer<support::big>(OS).write<uint32_t>(Bits); - } + support::endian::write<uint32_t>(OS, Bits, E); break; case 8: // If we emit a pair of instructions, the first one is // always in the top 32 bits, even on little-endian. - if (IsLittleEndian) { - uint64_t Swapped = (Bits << 32) | (Bits >> 32); - support::endian::Writer<support::little>(OS).write<uint64_t>(Swapped); - } else { - support::endian::Writer<support::big>(OS).write<uint64_t>(Bits); - } + support::endian::write<uint32_t>(OS, Bits >> 32, E); + support::endian::write<uint32_t>(OS, Bits, E); break; default: llvm_unreachable("Invalid instruction size"); |

