diff options
| author | Sanjay Patel <spatel@rotateright.com> | 2016-09-14 16:05:51 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2016-09-14 16:05:51 +0000 |
| commit | b1f0a0f4a88641779e2020b214c64aa9f2d225e9 (patch) | |
| tree | 404cd876bcfbb86e2b7caae5c149e3ca72911886 /llvm/lib/Target/PowerPC | |
| parent | 9bd42810064a6eccbb52f176011b43c7a02c65ef (diff) | |
| download | bcm5719-llvm-b1f0a0f4a88641779e2020b214c64aa9f2d225e9.tar.gz bcm5719-llvm-b1f0a0f4a88641779e2020b214c64aa9f2d225e9.zip | |
getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI
llvm-svn: 281493
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 91eb0514ed1..8b5fc515189 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -3200,7 +3200,7 @@ SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) { Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ && isa<ConstantSDNode>(Op0.getOperand(1))) { - unsigned Bits = Op0.getValueType().getSizeInBits(); + unsigned Bits = Op0.getValueSizeInBits(); if (b != Bits/8-1) return false; if (Op0.getConstantOperandVal(1) != Bits-8) @@ -3228,9 +3228,9 @@ SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) { // Now we need to make sure that the upper bytes are known to be // zero. - unsigned Bits = Op0.getValueType().getSizeInBits(); - if (!CurDAG->MaskedValueIsZero(Op0, - APInt::getHighBitsSet(Bits, Bits - (b+1)*8))) + unsigned Bits = Op0.getValueSizeInBits(); + if (!CurDAG->MaskedValueIsZero( + Op0, APInt::getHighBitsSet(Bits, Bits - (b + 1) * 8))) return false; LHS = Op0.getOperand(0); @@ -3263,7 +3263,7 @@ SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) { } else if (Op.getOpcode() == ISD::SRL) { if (!isa<ConstantSDNode>(Op.getOperand(1))) return false; - unsigned Bits = Op.getValueType().getSizeInBits(); + unsigned Bits = Op.getValueSizeInBits(); if (b != Bits/8-1) return false; if (Op.getConstantOperandVal(1) != Bits-8) diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 41c0387c6ce..cd75474a76a 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -4218,7 +4218,7 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) { int Offset = ArgOffset + SPDiff; - uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; + uint32_t OpSize = (Arg.getValueSizeInBits() + 7) / 8; int FI = MF.getFrameInfo().CreateFixedObject(OpSize, Offset, true); EVT VT = isPPC64 ? MVT::i64 : MVT::i32; SDValue FIN = DAG.getFrameIndex(FI, VT); |
