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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-26 15:39:40 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-04-26 15:39:40 +0000 |
| commit | 48b949b6501317a9ca21526d42d155c56fa7253f (patch) | |
| tree | 1761aa127167d569722b62f31d0593683069d30d /llvm/lib/Target/PowerPC | |
| parent | fa451ba1b982040a47917b27c855e85640246270 (diff) | |
| download | bcm5719-llvm-48b949b6501317a9ca21526d42d155c56fa7253f.tar.gz bcm5719-llvm-48b949b6501317a9ca21526d42d155c56fa7253f.zip | |
PowerPC: Fix encoding of stfsu and stfdu instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong sub-opcodes). Note that apparently
the compiler currently never generates pre-inc instructions
for floating point types for some reason ...
Tests will be added together with the asm parser.
llvm-svn: 180607
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 6d8ef6bb6a8..8bb5ae38785 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -1165,10 +1165,10 @@ def STHU : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), def STWU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins GPRC:$rS, memri:$dst), "stwu $rS, $dst", LdStStoreUpd, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STFSU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst), +def STFSU : DForm_1<53, (outs ptr_rc_nor0:$ea_res), (ins F4RC:$rS, memri:$dst), "stfsu $rS, $dst", LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; -def STFDU : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst), +def STFDU : DForm_1<55, (outs ptr_rc_nor0:$ea_res), (ins F8RC:$rS, memri:$dst), "stfdu $rS, $dst", LdStSTFDU, []>, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; } |

