Support to provide exception and selector registers.

llvm-svn: 34482

3 files changed, 40 insertions, 1 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index f8c970e88da..9c2867e87ad 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2610,6 +2610,30 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
   }
 }
 
+/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
+/// register.  The register was made live in the ISel.
+static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG &DAG) {
+  const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+                                 getTargetMachine().
+                                 getRegisterInfo();
+  MVT::ValueType VT = Op.Val->getValueType(0);
+  unsigned Reg = MRI->getEHExceptionRegister();
+  SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
+  return Result.getValue(Op.ResNo);
+}
+
+/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
+/// selection register.  The register was made live in the ISel.
+static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG &DAG) {
+  const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
+                                 getTargetMachine().
+                                 getRegisterInfo();
+  MVT::ValueType VT = Op.Val->getValueType(0);
+  unsigned Reg = MRI->getEHHandlerRegister();
+  SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
+  return Result.getValue(Op.ResNo);
+}
+
 /// LowerOperation - Provide custom lowering hooks for some operations.
 ///
 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
@@ -2647,6 +2671,10 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
   // Frame & Return address.  Currently unimplemented
   case ISD::RETURNADDR:         break;
   case ISD::FRAMEADDR:          break;
+  
+  // Exception address and exception selector.
+  case ISD::EXCEPTIONADDR:      return LowerEXCEPTIONADDR(Op, DAG);
+  case ISD::EHSELECTION:        return LowerEHSELECTION(Op, DAG);
   }
   return SDOperand();
 }
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7553634066e..38e57da1dd8 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1022,7 +1022,6 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
 
 unsigned PPCRegisterInfo::getRARegister() const {
   return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
-  
 }
 
 unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
@@ -1040,5 +1039,13 @@ void PPCRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
   Moves.push_back(MachineMove(0, Dst, Src));
 }
 
+unsigned PPCRegisterInfo::getEHExceptionRegister() const {
+  return !Subtarget.isPPC64() ? PPC::R3 : PPC::X3;
+}
+
+unsigned PPCRegisterInfo::getEHHandlerRegister() const {
+  return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
+}
+
 #include "PPCGenRegisterInfo.inc"
 
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 6c30f6b2a5d..eedb62770e8 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -89,6 +89,10 @@ public:
   unsigned getRARegister() const;
   unsigned getFrameRegister(MachineFunction &MF) const;
   void getInitialFrameState(std::vector<MachineMove> &Moves) const;
+
+  // Exception handling queries.
+  unsigned getEHExceptionRegister() const;
+  unsigned getEHHandlerRegister() const;
 };
 
 } // end namespace llvm