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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-12-02 08:32:59 -0600 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-12-02 08:56:04 -0600 |
| commit | 241cbf201a6f4b7658697e3c76fc6e741d049a01 (patch) | |
| tree | 2cf78b10e269e77a92830a23eea5a5d946cce757 /llvm/lib/Target/PowerPC | |
| parent | dcf11c5e86cee94ec649a7a31c5dd259f60579d6 (diff) | |
| download | bcm5719-llvm-241cbf201a6f4b7658697e3c76fc6e741d049a01.tar.gz bcm5719-llvm-241cbf201a6f4b7658697e3c76fc6e741d049a01.zip | |
[PowerPC] Fix crash in peephole optimization
When converting reg+reg shifts to reg+imm rotates, we neglect to consider the
CodeGenOnly versions of the 32-bit shift mnemonics. This means we produce a
rotate with missing operands which causes a crash.
Committing this fix without review since it is non-controversial that the list
of mnemonics to consider should include the 64-bit aliases for the exact
mnemonics.
Fixes PR44183.
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index e94ef4b1e50..f5e2b473f1e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -3757,8 +3757,10 @@ bool PPCInstrInfo::transformToImmFormFedByLI(MachineInstr &MI, ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg(); unsigned Opc = MI.getOpcode(); - bool SpecialShift32 = - Opc == PPC::SLW || Opc == PPC::SLWo || Opc == PPC::SRW || Opc == PPC::SRWo; + bool SpecialShift32 = Opc == PPC::SLW || Opc == PPC::SLWo || + Opc == PPC::SRW || Opc == PPC::SRWo || + Opc == PPC::SLW8 || Opc == PPC::SLW8o || + Opc == PPC::SRW8 || Opc == PPC::SRW8o; bool SpecialShift64 = Opc == PPC::SLD || Opc == PPC::SLDo || Opc == PPC::SRD || Opc == PPC::SRDo; bool SetCR = Opc == PPC::SLWo || Opc == PPC::SRWo || |
