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| author | Hal Finkel <hfinkel@anl.gov> | 2014-01-02 21:38:26 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2014-01-02 21:38:26 +0000 |
| commit | 1d429f2ee0fe16eb08d62a870767908f414b0062 (patch) | |
| tree | d7e240adc68fff96b3b3a306f2706182f3711413 /llvm/lib/Target/PowerPC | |
| parent | d8beca3b785bd3c9a68bf020443d2f226e9085ce (diff) | |
| download | bcm5719-llvm-1d429f2ee0fe16eb08d62a870767908f414b0062.tar.gz bcm5719-llvm-1d429f2ee0fe16eb08d62a870767908f414b0062.zip | |
[PPC] Fix the scheduling of CR logicals on the P7
CR logicals (crand, crxor, etc.) on the P7 need to be in the first slot of each
dispatch group. The old itinerary entry was just wrong (but has not mattered
because we don't generate these instructions).
This will matter when, in an upcoming commit, we start generating these
instructions.
llvm-svn: 198359
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleP7.td | 4 |
2 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 0c07fd33405..37c85b37351 100644 --- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -128,6 +128,7 @@ bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, default: // All multi-slot instructions must come first. return NSlots > 1; + case PPC::Sched::IIC_BrCR: // cr logicals case PPC::Sched::IIC_SprMFCR: case PPC::Sched::IIC_SprMFCRF: case PPC::Sched::IIC_SprMTSPR: diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP7.td b/llvm/lib/Target/PowerPC/PPCScheduleP7.td index 958bc90f674..a3670a55a04 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleP7.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleP7.td @@ -137,8 +137,8 @@ def P7Itineraries : ProcessorItineraries< InstrItinData<IIC_BrB , [InstrStage<1, [P7_DU5, P7_DU6], 0>, InstrStage<1, [P7_BRU]>], [3, 1, 1]>, - InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>, - InstrStage<1, [P7_BRU]>], + InstrItinData<IIC_BrCR , [InstrStage<1, [P7_DU1], 0>, + InstrStage<1, [P7_CRU]>], [3, 1, 1]>, InstrItinData<IIC_BrMCR , [InstrStage<1, [P7_DU5, P7_DU6], 0>, InstrStage<1, [P7_BRU]>], |
