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authorSean Fertile <sfertile@ca.ibm.com>2017-11-15 18:58:27 +0000
committerSean Fertile <sfertile@ca.ibm.com>2017-11-15 18:58:27 +0000
commit0f0837e84e16f0b88213b372ced02e9eb35fcf3c (patch)
tree2737d1d7daff7bc00e8ff9410b98f0a6d4b83252 /llvm/lib/Target/PowerPC
parent72b819b8ee0a0a5e0389028b4637a48c668798a9 (diff)
downloadbcm5719-llvm-0f0837e84e16f0b88213b372ced02e9eb35fcf3c.tar.gz
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[PowerPC] Implement mayBeEmittedAsTailCall for PPC
Implements TargetLowering callback 'mayBeEmittedAsTailCall' that enables CodeGenPrepare to duplicate returns when they might enable a tail-call. Differential Revision: https://reviews.llvm.org/D39777 llvm-svn: 318321
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp35
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.h4
2 files changed, 39 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 2d15b738a31..3c3657e1f56 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -13804,3 +13804,38 @@ SDValue PPCTargetLowering::combineSRL(SDNode *N, DAGCombinerInfo &DCI) const {
return SDValue();
}
+
+bool PPCTargetLowering::mayBeEmittedAsTailCall(const CallInst *CI) const {
+ // Only duplicate to increase tail-calls for the 64bit SysV ABIs.
+ if (!Subtarget.isSVR4ABI() || !Subtarget.isPPC64())
+ return false;
+
+ // If not a tail call then no need to proceed.
+ if (!CI->isTailCall())
+ return false;
+
+ // If tail calls are disabled for the caller then we are done.
+ const Function *Caller = CI->getParent()->getParent();
+ auto Attr = Caller->getFnAttribute("disable-tail-calls");
+ if (Attr.getValueAsString() == "true")
+ return false;
+
+ // If sibling calls have been disabled and tail-calls aren't guaranteed
+ // there is no reason to duplicate.
+ auto &TM = getTargetMachine();
+ if (!TM.Options.GuaranteedTailCallOpt && DisableSCO)
+ return false;
+
+ // Can't tail call a function called indirectly, or if it has variadic args.
+ const Function *Callee = CI->getCalledFunction();
+ if (!Callee || Callee->isVarArg())
+ return false;
+
+ // Make sure the callee and caller calling conventions are eligible for tco.
+ if (!areCallingConvEligibleForTCO_64SVR4(Caller->getCallingConv(),
+ CI->getCallingConv()))
+ return false;
+
+ // If the function is local then we have a good chance at tail-calling it
+ return getTargetMachine().shouldAssumeDSOLocal(*Caller->getParent(), Callee);
+}
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.h b/llvm/lib/Target/PowerPC/PPCISelLowering.h
index bf9c4b8e63b..c75b95691d5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.h
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.h
@@ -1085,6 +1085,10 @@ namespace llvm {
/// essentially v16i8 vector version of VINSERTH.
SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
+ // Return whether the call instruction can potentially be optimized to a
+ // tail call. This will cause the optimizers to attempt to move, or
+ // duplicate return instructions to help enable tail call optimizations.
+ bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
}; // end class PPCTargetLowering
namespace PPC {
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