-Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed

stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 2c116363886..3920b381509 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -2225,7 +2225,7 @@ struct TailCallArgumentInfo {
 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
 static void
 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
-                                  SDValue Chain,
+                                           SDValue Chain,
                    const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
                    SmallVector<SDValue, 8> &MemOpChains,
                    DebugLoc dl) {
@@ -3388,7 +3388,7 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
 
   // STD the extended value into the stack slot.
   MachineMemOperand *MMO =
-    MF.getMachineMemOperand(PseudoSourceValue::getStack(),
+    MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
                             MachineMemOperand::MOStore, 0, 8, 8);
   SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
   SDValue Store =