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authorHal Finkel <hfinkel@anl.gov>2016-03-31 20:39:41 +0000
committerHal Finkel <hfinkel@anl.gov>2016-03-31 20:39:41 +0000
commitfc35391f2b4c36ec1a35d6e464ad972cf7117cdb (patch)
tree026da57fa59dce0a2c65203543f5e5c01e23d310 /llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
parent132cd621216b7b09a170b9f10aa7494a87ce82fc (diff)
downloadbcm5719-llvm-fc35391f2b4c36ec1a35d6e464ad972cf7117cdb.tar.gz
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[PowerPC] Add a late MI-level pass for QPX load/splat simplification
Chapter 3 of the QPX manual states that, "Scalar floating-point load instructions, defined in the Power ISA, cause a replication of the source data across all elements of the target register." Thus, if we have a load followed by a QPX splat (from the first lane), the splat is redundant. This adds a late MI-level pass to remove the redundant splats in some of these cases (specifically when both occur in the same basic block). This optimization is scheduled just prior to post-RA scheduling. It can't happen before anything that might replace the load with some already-computed quantity (i.e. store-to-load forwarding). llvm-svn: 265047
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCTargetMachine.cpp13
1 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
index 8d5af9458be..5d47e0e3ebd 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -43,6 +43,10 @@ opt<bool> DisableVSXSwapRemoval("disable-ppc-vsx-swap-removal", cl::Hidden,
cl::desc("Disable VSX Swap Removal for PPC"));
static cl::
+opt<bool> DisableQPXLoadSplat("disable-ppc-qpx-load-splat", cl::Hidden,
+ cl::desc("Disable QPX load splat simplification"));
+
+static cl::
opt<bool> DisableMIPeephole("disable-ppc-peephole", cl::Hidden,
cl::desc("Disable machine peepholes for PPC"));
@@ -388,8 +392,15 @@ void PPCPassConfig::addPreRegAlloc() {
}
void PPCPassConfig::addPreSched2() {
- if (getOptLevel() != CodeGenOpt::None)
+ if (getOptLevel() != CodeGenOpt::None) {
addPass(&IfConverterID);
+
+ // This optimization must happen after anything that might do store-to-load
+ // forwarding. Here we're after RA (and, thus, when spills are inserted)
+ // but before post-RA scheduling.
+ if (!DisableQPXLoadSplat)
+ addPass(createPPCQPXLoadSplatPass());
+ }
}
void PPCPassConfig::addPreEmitPass() {
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