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author | Hal Finkel <hfinkel@anl.gov> | 2016-10-02 02:10:20 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2016-10-02 02:10:20 +0000 |
commit | a9321059b912155cd81cf0776d54a7d6838ef7ab (patch) | |
tree | 9706bfa174d683caf0884092ed577f48b7699075 /llvm/lib/Target/PowerPC/PPCSubtarget.h | |
parent | 1f7b813e2b32e72136050558b60f5d90ae2ee4b2 (diff) | |
download | bcm5719-llvm-a9321059b912155cd81cf0776d54a7d6838ef7ab.tar.gz bcm5719-llvm-a9321059b912155cd81cf0776d54a7d6838ef7ab.zip |
[PowerPC] Refactor soft-float support, and enable PPC64 soft float
This change enables soft-float for PowerPC64, and also makes soft-float disable
all vector instruction sets for both 32-bit and 64-bit modes. This latter part
is necessary because the PPC backend canonicalizes many Altivec vector types to
floating-point types, and so soft-float breaks scalarization support for many
operations. Both for embedded targets and for operating-system kernels desiring
soft-float support, it seems reasonable that disabling hardware floating-point
also disables vector instructions (embedded targets without hardware floating
point support are unlikely to have Altivec, etc. and operating system kernels
desiring not to use floating-point registers to lower syscall cost are unlikely
to want to use vector registers either). If someone needs this to work, we'll
need to change the fact that we promote many Altivec operations to act on
v4f32. To make it possible to disable Altivec when soft-float is enabled,
hardware floating-point support needs to be expressed as a positive feature,
like the others, and not a negative feature, because target features cannot
have dependencies on the disabling of some other feature. So +soft-float has
now become -hard-float.
Fixes PR26970.
llvm-svn: 283060
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCSubtarget.h')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCSubtarget.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index d80a9ad8d34..7fd907990ce 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -91,7 +91,7 @@ protected: bool Has64BitSupport; bool Use64BitRegs; bool UseCRBits; - bool UseSoftFloat; + bool HasHardFloat; bool IsPPC64; bool HasAltivec; bool HasSPE; @@ -205,7 +205,7 @@ public: /// instructions, regardless of whether we are in 32-bit or 64-bit mode. bool has64BitSupport() const { return Has64BitSupport; } // useSoftFloat - Return true if soft-float option is turned on. - bool useSoftFloat() const { return UseSoftFloat; } + bool useSoftFloat() const { return !HasHardFloat; } /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit /// registers in 32-bit mode when possible. This can only true if |