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| author | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-16 17:34:12 +0000 |
| commit | a35f306740182bd02191f573983dbea0a0036ecd (patch) | |
| tree | dda049ba457302630fb70f8c45e33d3a44c95b61 /llvm/lib/Target/PowerPC/PPCSubtarget.h | |
| parent | 29052c849fac31468cea718890c90026fd177072 (diff) | |
| download | bcm5719-llvm-a35f306740182bd02191f573983dbea0a0036ecd.tar.gz bcm5719-llvm-a35f306740182bd02191f573983dbea0a0036ecd.zip | |
Rename some subtarget features. A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.
llvm-svn: 28824
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCSubtarget.h')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCSubtarget.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h index c98291e1620..e898a048c6c 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.h +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h @@ -33,8 +33,8 @@ protected: /// Used by the ISel to turn in optimizations for POWER4-derived architectures bool IsGigaProcessor; - bool Is64Bit; - bool Has64BitRegs; + bool Has64BitSupport; + bool Use64BitRegs; bool HasAltivec; bool HasFSQRT; bool HasSTFIWX; @@ -66,12 +66,12 @@ public: bool hasFSQRT() const { return HasFSQRT; } bool hasSTFIWX() const { return HasSTFIWX; } - bool has64BitRegs() const { return Has64BitRegs; } + bool use64BitRegs() const { return Use64BitRegs; } bool hasAltivec() const { return HasAltivec; } bool isAIX() const { return IsAIX; } bool isDarwin() const { return IsDarwin; } - bool is64Bit() const { return Is64Bit; } + bool has64BitSupport() const { return Has64BitSupport; } bool isGigaProcessor() const { return IsGigaProcessor; } }; } // End llvm namespace |
