Give full control of subtarget features over to table generated code.

llvm-svn: 24013

1 files changed, 7 insertions, 1 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.h b/llvm/lib/Target/PowerPC/PPCSubtarget.h
index 9d0edf54ffb..5e94612da7a 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.h
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.h
@@ -31,6 +31,7 @@ protected:
   bool IsGigaProcessor;
   bool Is64Bit;
   bool Has64BitRegs;
+  bool HasAltivec;
   bool HasFSQRT;
   bool IsAIX;
   bool IsDarwin;
@@ -39,6 +40,10 @@ public:
   /// of the specified module.
   ///
   PPCSubtarget(const Module &M, const std::string &FS);
+  
+  /// ParseSubtargetFeatures - Parses features string setting specified 
+  /// subtarget options.  Definition of function is usto generated by tblgen.
+  void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU);
 
   /// getStackAlignment - Returns the minimum alignment known to hold of the
   /// stack frame on entry to the function and which must be maintained by every
@@ -46,11 +51,12 @@ public:
   unsigned getStackAlignment() const { return StackAlignment; }
 
   bool hasFSQRT() const { return HasFSQRT; }
+  bool has64BitRegs() const { return Has64BitRegs; }
+  bool hasAltivec() const { return HasAltivec; }
   
   bool isAIX() const { return IsAIX; }
   bool isDarwin() const { return IsDarwin; }
   bool is64Bit() const { return Is64Bit; }
-  bool has64BitRegs() const { return Has64BitRegs; }
   bool isGigaProcessor() const { return IsGigaProcessor; }
 };
 } // End llvm namespace