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| author | Hal Finkel <hfinkel@anl.gov> | 2012-04-01 04:44:16 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-04-01 04:44:16 +0000 |
| commit | 59607e63cbb2d69820ae1007e77379952fcbbefd (patch) | |
| tree | 21a1a3e3e5b9d644047aa3dfa2ca9c26e346d3c4 /llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td | |
| parent | 1eaae507341bd15b2861c4f32245b5418e5fe69f (diff) | |
| download | bcm5719-llvm-59607e63cbb2d69820ae1007e77379952fcbbefd.tar.gz bcm5719-llvm-59607e63cbb2d69820ae1007e77379952fcbbefd.zip | |
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
llvm-svn: 153821
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td b/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td index f76557afc8b..37ebfc59880 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleG4Plus.td @@ -34,7 +34,8 @@ def G4PlusItineraries : ProcessorItineraries< InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, - InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>, + InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, + InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, InstrItinData<LdStUX , [InstrStage<3, [SLU]>]>, |
