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author | Jim Laskey <jlaskey@mac.com> | 2005-10-18 16:23:40 +0000 |
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committer | Jim Laskey <jlaskey@mac.com> | 2005-10-18 16:23:40 +0000 |
commit | c6533006c869aa6848b1ff687189aa457db86a3d (patch) | |
tree | 82165c74b1b3eb671abce3f39cf216effe5e00a8 /llvm/lib/Target/PowerPC/PPCScheduleG4.td | |
parent | 53b9c3ad4c785f4cb77e6d974719083045a4351f (diff) | |
download | bcm5719-llvm-c6533006c869aa6848b1ff687189aa457db86a3d.tar.gz bcm5719-llvm-c6533006c869aa6848b1ff687189aa457db86a3d.zip |
Checking in first round of scheduling tablegen files. Not tied in as yet.
llvm-svn: 23786
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCScheduleG4.td')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleG4.td | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG4.td b/llvm/lib/Target/PowerPC/PPCScheduleG4.td new file mode 100644 index 00000000000..28fb004f625 --- /dev/null +++ b/llvm/lib/Target/PowerPC/PPCScheduleG4.td @@ -0,0 +1,88 @@ +//===- PPCScheduleG4.td - PPC G4 Scheduling Definitions ----*- tablegen -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by James M. Laskey and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the itinerary class data for the G4 (7400) processor. +// +//===----------------------------------------------------------------------===// + +def G4Itineraries : ProcessorItineraries<G4, [ + InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, + InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, + InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, + InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>, + InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>, + InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>, + InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>, + InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>, + InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>, + InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>, + InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>, + InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>, + InstrItinData<BrB , [InstrStage<1, [BPU]>]>, + InstrItinData<BrCR , [InstrStage<1, [SRU]>]>, + InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>, + InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, + InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, + InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLWA , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, + InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStSTD , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStSTDCX , [InstrStage<0, [NoUnit]>]>, + InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>, + InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>, + InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>, + InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>, + InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>, + InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>, + InstrItinData<SprTLBSYNC , [InstrStage<8, [SRU]>]>, + InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>, + InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>, + InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>, + InstrItinData<SprMFTB , [InstrStage<1, [SRU]>]>, + InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>, + InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>, + InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>, + InstrItinData<SprSC , [InstrStage<2, [SRU]>]>, + InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>, + InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>, + InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>, + InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>, + InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>, + InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>, + InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>, + InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, + InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, + InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>, + InstrItinData<VecComplex , [InstrStage<3, [VIU2]>]>, + InstrItinData<VecPerm , [InstrStage<1, [VPU]>]>, + InstrItinData<VecFPRound , [InstrStage<4, [VFPU]>]>, + InstrItinData<VecVSL , [InstrStage<1, [VIU1]>]>, + InstrItinData<VecVSR , [InstrStage<1, [VIU1]>]> +]>; |