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authorHal Finkel <hfinkel@anl.gov>2012-06-12 19:01:24 +0000
committerHal Finkel <hfinkel@anl.gov>2012-06-12 19:01:24 +0000
commit8c33dde66657721f21b76470e2be3b519d4ba594 (patch)
tree83506d8b4056b52f198e6776ef1bef9cd6499652 /llvm/lib/Target/PowerPC/PPCScheduleG4.td
parent6d6baa88f65ac6ae68f4bc4f81afa3d9f9b83299 (diff)
downloadbcm5719-llvm-8c33dde66657721f21b76470e2be3b519d4ba594.tar.gz
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Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled in the load/store pipelines. We'll call these IntSimple. llvm-svn: 158366
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCScheduleG4.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCScheduleG4.td1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG4.td b/llvm/lib/Target/PowerPC/PPCScheduleG4.td
index f7ec1e01333..e19ddfa80ea 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleG4.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleG4.td
@@ -13,6 +13,7 @@
def G4Itineraries : ProcessorItineraries<
[IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [
+ InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>,
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