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| author | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-10-19 19:51:16 +0000 |
| commit | 74ab9960f2943ea951fbc10ad48ca8f5ec2ca035 (patch) | |
| tree | 974889776050113ad3b3e889399dc51b52675802 /llvm/lib/Target/PowerPC/PPCScheduleG4.td | |
| parent | b2544ff7a7f22392bc681df7d6e4857f4ff38cec (diff) | |
| download | bcm5719-llvm-74ab9960f2943ea951fbc10ad48ca8f5ec2ca035.tar.gz bcm5719-llvm-74ab9960f2943ea951fbc10ad48ca8f5ec2ca035.zip | |
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCScheduleG4.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleG4.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleG4.td b/llvm/lib/Target/PowerPC/PPCScheduleG4.td index 2b1818a24fb..d0e445605f4 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleG4.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleG4.td @@ -30,15 +30,15 @@ def G4Itineraries : ProcessorItineraries<[ InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStDCBT , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStGeneral , [InstrStage<2, [SLU]>]>, InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>, InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>, - InstrItinData<LdStLBZUX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStUX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, - InstrItinData<LdStLVEBX , [InstrStage<2, [SLU]>]>, + InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>, InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>, |
