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| author | Hal Finkel <hfinkel@anl.gov> | 2012-06-12 19:01:24 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-06-12 19:01:24 +0000 |
| commit | 8c33dde66657721f21b76470e2be3b519d4ba594 (patch) | |
| tree | 83506d8b4056b52f198e6776ef1bef9cd6499652 /llvm/lib/Target/PowerPC/PPCScheduleA2.td | |
| parent | 6d6baa88f65ac6ae68f4bc4f81afa3d9f9b83299 (diff) | |
| download | bcm5719-llvm-8c33dde66657721f21b76470e2be3b519d4ba594.tar.gz bcm5719-llvm-8c33dde66657721f21b76470e2be3b519d4ba594.zip | |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
llvm-svn: 158366
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCScheduleA2.td')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCScheduleA2.td | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleA2.td b/llvm/lib/Target/PowerPC/PPCScheduleA2.td index 20e869d62ee..ef41a05df32 100644 --- a/llvm/lib/Target/PowerPC/PPCScheduleA2.td +++ b/llvm/lib/Target/PowerPC/PPCScheduleA2.td @@ -60,6 +60,17 @@ def PPCA2Itineraries : ProcessorItineraries< IU5, IU6, RF0, XRF1, XEX1, XEX2, XEX3, XEX4, XEX5, XEX6, FRF1, FEX1, FEX2, FEX3, FEX4, FEX5, FEX6], [CR_Bypass, GPR_Bypass, FPR_Bypass], [ + InstrItinData<IntSimple , [InstrStage<4, + [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, + InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, + IU4_4, IU4_5, IU4_6, IU4_7]>, + InstrStage<1, [IU5]>, InstrStage<1, [IU6]>, + InstrStage<1, [RF0]>, InstrStage<1, [XRF1]>, + InstrStage<1, [XEX1]>, InstrStage<1, [XEX2]>, + InstrStage<1, [XEX3]>, InstrStage<1, [XEX4]>, + InstrStage<1, [XEX5]>, InstrStage<1, [XEX6]>], + [10, 7, 7], + [GPR_Bypass, GPR_Bypass, GPR_Bypass]>, InstrItinData<IntGeneral , [InstrStage<4, [IU0to3_0, IU0to3_1, IU0to3_2, IU0to3_3]>, InstrStage<1, [IU4_0, IU4_1, IU4_2, IU4_3, |
