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| author | Andrew Trick <atrick@apple.com> | 2013-03-16 18:58:55 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-03-16 18:58:55 +0000 |
| commit | bf8a28dc523bc0bfb6d781f16f7fc16c8f5bad81 (patch) | |
| tree | fe2b7b168fc92feb0624a48214e90015c359b683 /llvm/lib/Target/PowerPC/PPCRegisterInfo.h | |
| parent | 6d88a690e6caf98e4a9e01471f257b5affb5b149 (diff) | |
| download | bcm5719-llvm-bf8a28dc523bc0bfb6d781f16f7fc16c8f5bad81.tar.gz bcm5719-llvm-bf8a28dc523bc0bfb6d781f16f7fc16c8f5bad81.zip | |
Machine model. Allow mixed itinerary classes and SchedRW lists.
We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.
Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.
llvm-svn: 177226
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.h')
0 files changed, 0 insertions, 0 deletions
