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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 19:03:21 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 19:03:21 +0000 |
| commit | a1431df540e16be6d7c2ddd74b7b78505b95e3f9 (patch) | |
| tree | 290c465a0caa6a5647f6b31e20d05fc9ff84add5 /llvm/lib/Target/PowerPC/PPCRegisterInfo.h | |
| parent | aa03c03a2d7a38bc9f1361246c8d91033264b930 (diff) | |
| download | bcm5719-llvm-a1431df540e16be6d7c2ddd74b7b78505b95e3f9.tar.gz bcm5719-llvm-a1431df540e16be6d7c2ddd74b7b78505b95e3f9.zip | |
Add support for spilling VRSAVE on PPC
Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.
llvm-svn: 177654
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.h')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h index 5f89f630ed9..1c020ea5c93 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h @@ -66,6 +66,11 @@ public: int SPAdj, RegScavenger *RS) const; void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex, int SPAdj, RegScavenger *RS) const; + void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, + int SPAdj, RegScavenger *RS) const; + void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex, + int SPAdj, RegScavenger *RS) const; + bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const; void eliminateFrameIndex(MachineBasicBlock::iterator II, |
