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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 23:45:03 +0000 |
| commit | f70c41ea7c524dd78b154490a7479244f19f63f4 (patch) | |
| tree | 92e974304922be160c6199ee8925c0188f5958fb /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | cdd21b333a9b495f41fda81b5240360dcba06f7a (diff) | |
| download | bcm5719-llvm-f70c41ea7c524dd78b154490a7479244f19f63f4.tar.gz bcm5719-llvm-f70c41ea7c524dd78b154490a7479244f19f63f4.zip | |
Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.
No functionality change intended.
llvm-svn: 177683
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 150e2411618..75e20e4a269 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -125,6 +125,7 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { // The ZERO register is not really a register, but the representation of r0 // when used in instructions that treat r0 as the constant 0. Reserved.set(PPC::ZERO); + Reserved.set(PPC::ZERO8); // The FP register is also not really a register, but is the representation // of the frame pointer register used by ISD::FRAMEADDR. |
