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| author | Zaara Syeda <syzaara@ca.ibm.com> | 2018-01-17 20:00:15 +0000 |
|---|---|---|
| committer | Zaara Syeda <syzaara@ca.ibm.com> | 2018-01-17 20:00:15 +0000 |
| commit | c9dc7b451b48be78681627a90339b4e7ee66fcb8 (patch) | |
| tree | 8758ebc7f35542af3311cf7d8f510d3e64c58aeb /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | f5ff5d584ebbbbe63e3b24f194df7b5942b43adb (diff) | |
| download | bcm5719-llvm-c9dc7b451b48be78681627a90339b4e7ee66fcb8.tar.gz bcm5719-llvm-c9dc7b451b48be78681627a90339b4e7ee66fcb8.zip | |
Revert [PowerPC] This reverts commit rL322721
Failing build bots. Revert the commit now.
llvm-svn: 322748
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index a938bb98ce1..6b62a82ef7b 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -144,17 +144,6 @@ PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { // On PPC64, we might need to save r2 (but only if it is not reserved). bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2); - if (MF->getFunction().getCallingConv() == CallingConv::Cold) { - return TM.isPPC64() - ? (Subtarget.hasAltivec() - ? (SaveR2 ? CSR_SVR64_ColdCC_R2_Altivec_SaveList - : CSR_SVR64_ColdCC_Altivec_SaveList) - : (SaveR2 ? CSR_SVR64_ColdCC_R2_SaveList - : CSR_SVR64_ColdCC_SaveList)) - : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_SaveList - : CSR_SVR32_ColdCC_SaveList); - } - return TM.isPPC64() ? (Subtarget.hasAltivec() ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList @@ -207,13 +196,6 @@ PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask : CSR_Darwin32_RegMask); - if (CC == CallingConv::Cold) { - return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask - : CSR_SVR64_ColdCC_RegMask) - : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask - : CSR_SVR32_ColdCC_RegMask); - } - return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask : CSR_SVR464_RegMask) : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask |
