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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-19 14:46:07 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-19 14:46:07 +0000 |
| commit | 30c38c38497763d5660fde146e1185c0dbb082d5 (patch) | |
| tree | 4ab35d4a334b1c9129e18e7ad03fdaa2700bd28e /llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 10fe9bc79eb38319cf6faf7fe4ffe131b23419af (diff) | |
| download | bcm5719-llvm-30c38c38497763d5660fde146e1185c0dbb082d5.tar.gz bcm5719-llvm-30c38c38497763d5660fde146e1185c0dbb082d5.zip | |
[X86] Generalize schedule classes to support multiple stages
Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults.
This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases.
I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific.
Differential Revision: https://reviews.llvm.org/D44612
llvm-svn: 327855
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp')
0 files changed, 0 insertions, 0 deletions
