summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
diff options
context:
space:
mode:
authorTim Shen <timshen91@gmail.com>2017-09-22 18:30:02 +0000
committerTim Shen <timshen91@gmail.com>2017-09-22 18:30:02 +0000
commitcee75361885c50744afbc9ee4918c28e4210086f (patch)
treee19f16db39283594e8db88e350b7c3dda3de20b9 /llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
parent7725e497d10931a562a6263ce353d8eacf11e14b (diff)
downloadbcm5719-llvm-cee75361885c50744afbc9ee4918c28e4210086f.tar.gz
bcm5719-llvm-cee75361885c50744afbc9ee4918c28e4210086f.zip
[XRay] support conditional return on PPC.
Summary: Conditional returns were not taken into consideration at all. Implement them by turning them into jumps and normal returns. This means there is a slightly higher performance penalty for conditional returns, but this is the best we can do, and it still disturbs little of the rest. Reviewers: dberris, echristo Subscribers: sanjoy, nemanjai, hiraditya, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D38102 llvm-svn: 314005
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCMCInstLower.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCMCInstLower.cpp81
1 files changed, 42 insertions, 39 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
index b310493587a..cde511cb2e6 100644
--- a/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
+++ b/llvm/lib/Target/PowerPC/PPCMCInstLower.cpp
@@ -143,45 +143,48 @@ void llvm::LowerPPCMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- const MachineOperand &MO = MI->getOperand(i);
-
MCOperand MCOp;
- switch (MO.getType()) {
- default:
- MI->print(errs());
- llvm_unreachable("unknown operand type");
- case MachineOperand::MO_Register:
- assert(!MO.getSubReg() && "Subregs should be eliminated!");
- assert(MO.getReg() > PPC::NoRegister &&
- MO.getReg() < PPC::NUM_TARGET_REGS &&
- "Invalid register for this target!");
- MCOp = MCOperand::createReg(MO.getReg());
- break;
- case MachineOperand::MO_Immediate:
- MCOp = MCOperand::createImm(MO.getImm());
- break;
- case MachineOperand::MO_MachineBasicBlock:
- MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
- MO.getMBB()->getSymbol(), AP.OutContext));
- break;
- case MachineOperand::MO_GlobalAddress:
- case MachineOperand::MO_ExternalSymbol:
- MCOp = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP, isDarwin);
- break;
- case MachineOperand::MO_JumpTableIndex:
- MCOp = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, isDarwin);
- break;
- case MachineOperand::MO_ConstantPoolIndex:
- MCOp = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, isDarwin);
- break;
- case MachineOperand::MO_BlockAddress:
- MCOp = GetSymbolRef(MO,AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP,
- isDarwin);
- break;
- case MachineOperand::MO_RegisterMask:
- continue;
- }
-
- OutMI.addOperand(MCOp);
+ if (LowerPPCMachineOperandToMCOperand(MI->getOperand(i), MCOp, AP,
+ isDarwin))
+ OutMI.addOperand(MCOp);
+ }
+}
+
+bool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
+ MCOperand &OutMO, AsmPrinter &AP,
+ bool isDarwin) {
+ switch (MO.getType()) {
+ default:
+ llvm_unreachable("unknown operand type");
+ case MachineOperand::MO_Register:
+ assert(!MO.getSubReg() && "Subregs should be eliminated!");
+ assert(MO.getReg() > PPC::NoRegister &&
+ MO.getReg() < PPC::NUM_TARGET_REGS &&
+ "Invalid register for this target!");
+ OutMO = MCOperand::createReg(MO.getReg());
+ return true;
+ case MachineOperand::MO_Immediate:
+ OutMO = MCOperand::createImm(MO.getImm());
+ return true;
+ case MachineOperand::MO_MachineBasicBlock:
+ OutMO = MCOperand::createExpr(
+ MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext));
+ return true;
+ case MachineOperand::MO_GlobalAddress:
+ case MachineOperand::MO_ExternalSymbol:
+ OutMO = GetSymbolRef(MO, GetSymbolFromOperand(MO, AP), AP, isDarwin);
+ return true;
+ case MachineOperand::MO_JumpTableIndex:
+ OutMO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, isDarwin);
+ return true;
+ case MachineOperand::MO_ConstantPoolIndex:
+ OutMO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, isDarwin);
+ return true;
+ case MachineOperand::MO_BlockAddress:
+ OutMO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP,
+ isDarwin);
+ return true;
+ case MachineOperand::MO_RegisterMask:
+ return false;
}
}
OpenPOWER on IntegriCloud