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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-06-26 13:49:15 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-06-26 13:49:15 +0000
commitfd3ad693e8e84b2ad94f81c58992d7a8468861fc (patch)
treeaac5b09669dce49ce0cfa4fdfeca9d3bba513f79 /llvm/lib/Target/PowerPC/PPCInstrInfo.td
parenta6f5542be4463493dbbcb61d8c1b6c5936cbb938 (diff)
downloadbcm5719-llvm-fd3ad693e8e84b2ad94f81c58992d7a8468861fc.tar.gz
bcm5719-llvm-fd3ad693e8e84b2ad94f81c58992d7a8468861fc.zip
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic operands. However, for u16imm operands, we only support actual immediate integers. This causes the assembler to reject code like ori %r5, %r5, symbol@l This patch changes the u16imm operand definition to likewise accept symbolic operands. In fact, s16imm and u16imm can share the same encoding routine, now renamed to getImm16Encoding. llvm-svn: 184944
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index a9cfd5ef872..a9706967331 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -434,7 +434,7 @@ def PPCS16ImmAsmOperand : AsmOperandClass {
}
def s16imm : Operand<i32> {
let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getS16ImmEncoding";
+ let EncoderMethod = "getImm16Encoding";
let ParserMatchClass = PPCS16ImmAsmOperand;
}
def PPCU16ImmAsmOperand : AsmOperandClass {
@@ -443,6 +443,7 @@ def PPCU16ImmAsmOperand : AsmOperandClass {
}
def u16imm : Operand<i32> {
let PrintMethod = "printU16ImmOperand";
+ let EncoderMethod = "getImm16Encoding";
let ParserMatchClass = PPCU16ImmAsmOperand;
}
def PPCDirectBrAsmOperand : AsmOperandClass {
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