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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-04 14:24:00 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-04 14:24:00 +0000
commitb86cb7d04be194b37df4bfbb0e506736cf73de14 (patch)
tree429d8a80f718c17379a700821f4ac61800eb946a /llvm/lib/Target/PowerPC/PPCInstrInfo.td
parent371722288c33b3a6f1e576601d65dcce1c398646 (diff)
downloadbcm5719-llvm-b86cb7d04be194b37df4bfbb0e506736cf73de14.tar.gz
bcm5719-llvm-b86cb7d04be194b37df4bfbb0e506736cf73de14.zip
[PowerPC] Add asm parser support for CR expressions
This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". llvm-svn: 185633
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 022c15179b9..e104ea5ceb6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -392,7 +392,7 @@ def vrrc : RegisterOperand<VRRC> {
let ParserMatchClass = PPCRegVRRCAsmOperand;
}
def PPCRegCRBITRCAsmOperand : AsmOperandClass {
- let Name = "RegCRBITRC"; let PredicateMethod = "isRegNumber";
+ let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";
}
def crbitrc : RegisterOperand<CRBITRC> {
let ParserMatchClass = PPCRegCRBITRCAsmOperand;
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