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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-23 22:48:06 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-05-23 22:48:06 +0000
commit994854692340b98fb0ccedc41c384ac9664255be (patch)
tree2e975fd31bbb1baea6a732072b86bb551d994ad2 /llvm/lib/Target/PowerPC/PPCInstrInfo.td
parentfddddbeab033d2b53dc2dbd8e1da7f78349a8874 (diff)
downloadbcm5719-llvm-994854692340b98fb0ccedc41c384ac9664255be.tar.gz
bcm5719-llvm-994854692340b98fb0ccedc41c384ac9664255be.zip
[PowerPC] Remove symbolLo/symbolHi instruction operand types
Now that there is no longer any distinction between symbolLo and symbolHi operands in either printing, encoding, or parsing, the operand types can be removed in favor of simply using s16imm. This completes the patch series to decouple lo/hi operand part processing from the particular instruction whose operand it is. No change in code generation expected from this patch. llvm-svn: 182618
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCInstrInfo.td21
1 files changed, 6 insertions, 15 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 9a1a89ae9bc..a7e050d7791 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -434,6 +434,7 @@ def PPCS16ImmAsmOperand : AsmOperandClass {
}
def s16imm : Operand<i32> {
let PrintMethod = "printS16ImmOperand";
+ let EncoderMethod = "getS16ImmEncoding";
let ParserMatchClass = PPCS16ImmAsmOperand;
}
def PPCU16ImmAsmOperand : AsmOperandClass {
@@ -458,16 +459,6 @@ def calltarget : Operand<iPTR> {
def aaddr : Operand<iPTR> {
let PrintMethod = "printAbsAddrOperand";
}
-def symbolHi: Operand<i32> {
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getS16ImmEncoding";
- let ParserMatchClass = PPCS16ImmAsmOperand;
-}
-def symbolLo: Operand<i32> {
- let PrintMethod = "printS16ImmOperand";
- let EncoderMethod = "getS16ImmEncoding";
- let ParserMatchClass = PPCS16ImmAsmOperand;
-}
def PPCCRBitMaskOperand : AsmOperandClass {
let Name = "CRBitMask"; let PredicateMethod = "isCRBitMask";
}
@@ -1403,7 +1394,7 @@ def SYNC : XForm_24_sync<31, 598, (outs), (ins),
//
let PPC970_Unit = 1 in { // FXU Operations.
-def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$imm),
+def ADDI : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
"addi $rD, $rA, $imm", IntSimple,
[(set i32:$rD, (add i32:$rA, imm32SExt16:$imm))]>;
let BaseName = "addic" in {
@@ -1417,11 +1408,11 @@ def ADDICo : DForm_2<13, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
"addic. $rD, $rA, $imm", IntGeneral,
[]>, isDOT, RecFormRel;
}
-def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolHi:$imm),
+def ADDIS : DForm_2<15, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
"addis $rD, $rA, $imm", IntSimple,
[(set i32:$rD, (add i32:$rA, imm16ShiftedSExt:$imm))]>;
let isCodeGenOnly = 1 in
-def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, symbolLo:$sym),
+def LA : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$sym),
"la $rD, $sym($rA)", IntGeneral,
[(set i32:$rD, (add i32:$rA,
(PPClo tglobaladdr:$sym, 0)))]>;
@@ -1434,10 +1425,10 @@ def SUBFIC : DForm_2< 8, (outs gprc:$rD), (ins gprc:$rA, s16imm:$imm),
[(set i32:$rD, (subc imm32SExt16:$imm, i32:$rA))]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
- def LI : DForm_2_r0<14, (outs gprc:$rD), (ins symbolLo:$imm),
+ def LI : DForm_2_r0<14, (outs gprc:$rD), (ins s16imm:$imm),
"li $rD, $imm", IntSimple,
[(set i32:$rD, imm32SExt16:$imm)]>;
- def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins symbolHi:$imm),
+ def LIS : DForm_2_r0<15, (outs gprc:$rD), (ins s16imm:$imm),
"lis $rD, $imm", IntSimple,
[(set i32:$rD, imm16ShiftedSExt:$imm)]>;
}
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