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| author | Chen Zheng <czhengsz@cn.ibm.com> | 2019-01-30 23:18:38 +0000 |
|---|---|---|
| committer | Chen Zheng <czhengsz@cn.ibm.com> | 2019-01-30 23:18:38 +0000 |
| commit | be589423d8ea24370bb087a2a05f75100d1be76d (patch) | |
| tree | 4bfc36d63d5490a2641fa9792f94aaab2362e7f6 /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 8e7891544642c1326737c92be68edd1c90e7a660 (diff) | |
| download | bcm5719-llvm-be589423d8ea24370bb087a2a05f75100d1be76d.tar.gz bcm5719-llvm-be589423d8ea24370bb087a2a05f75100d1be76d.zip | |
[PowerPC] delete no more needed workaround for readsRegister() in PowerPC
Differential Revision: https://reviews.llvm.org/D57439
llvm-svn: 352689
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 14 |
1 files changed, 0 insertions, 14 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index ecc5e28c0d8..5952d73d205 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2357,13 +2357,6 @@ MachineInstr *PPCInstrInfo::getForwardingDefMI( MachineBasicBlock::reverse_iterator E = MI.getParent()->rend(), It = MI; It++; unsigned Reg = MI.getOperand(i).getReg(); - // MachineInstr::readsRegister only returns true if the machine - // instruction reads the exact register or its super-register. It - // does not consider uses of sub-registers which seems like strange - // behaviour. Nonetheless, if we end up with a 64-bit register here, - // get the corresponding 32-bit register to check. - if (PPC::G8RCRegClass.contains(Reg)) - Reg = Reg - PPC::X0 + PPC::R0; // Is this register defined by some form of add-immediate (including // load-immediate) within this basic block? @@ -3183,14 +3176,7 @@ bool PPCInstrInfo::isRegElgibleForForwarding(const MachineOperand &RegMO, if (MRI.isSSA()) return false; - // MachineInstr::readsRegister only returns true if the machine - // instruction reads the exact register or its super-register. It - // does not consider uses of sub-registers which seems like strange - // behaviour. Nonetheless, if we end up with a 64-bit register here, - // get the corresponding 32-bit register to check. unsigned Reg = RegMO.getReg(); - if (PPC::G8RCRegClass.contains(Reg)) - Reg = Reg - PPC::X0 + PPC::R0; // Walking the inst in reverse(MI-->DefMI) to get the last DEF of the Reg. MachineBasicBlock::const_reverse_iterator It = MI; |

