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| author | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-15 16:51:28 +0000 |
|---|---|---|
| committer | Hiroshi Inoue <inouehrs@jp.ibm.com> | 2017-06-15 16:51:28 +0000 |
| commit | 7a08bb145846730efc8a12ed1cb23a3534f30e72 (patch) | |
| tree | ec547a1dd1c279f70da79f14c38c5c5973028c13 /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | 24ca9da2dee135ef671f14707c709d17bd516498 (diff) | |
| download | bcm5719-llvm-7a08bb145846730efc8a12ed1cb23a3534f30e72.tar.gz bcm5719-llvm-7a08bb145846730efc8a12ed1cb23a3534f30e72.zip | |
[PowerPC] fix potential verification errors on CFENCE8
This patch fixes a potential verification error (64-bit register operands for cmpw) with -verify-machineinstrs.
Differential Revision: https://reviews.llvm.org/D34208
llvm-svn: 305479
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index f3c68c443b1..236e513bec2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1964,7 +1964,7 @@ bool PPCInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { } case PPC::CFENCE8: { auto Val = MI.getOperand(0).getReg(); - BuildMI(MBB, MI, DL, get(PPC::CMPW), PPC::CR7).addReg(Val).addReg(Val); + BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val); BuildMI(MBB, MI, DL, get(PPC::CTRL_DEP)) .addImm(PPC::PRED_NE_MINUS) .addReg(PPC::CR7) |
