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| author | Bill Wendling <isanbard@gmail.com> | 2013-06-07 07:55:53 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-06-07 07:55:53 +0000 |
| commit | 5e7656bf0cdc3261e5fcf8f778e563c751a62aec (patch) | |
| tree | fa692a388ad9f8b05505e217dd6749acdfbe02fd /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
| parent | ead89ef63e9de8069085f7fe908c64bb990bc4d9 (diff) | |
| download | bcm5719-llvm-5e7656bf0cdc3261e5fcf8f778e563c751a62aec.tar.gz bcm5719-llvm-5e7656bf0cdc3261e5fcf8f778e563c751a62aec.zip | |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
llvm-svn: 183494
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index d94acde101e..e2d870de04a 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -47,7 +47,7 @@ cl::desc("Disable compare instruction optimization"), cl::Hidden); PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), - TM(tm), RI(*TM.getSubtargetImpl(), *this) {} + TM(tm), RI(*TM.getSubtargetImpl()) {} /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. @@ -77,7 +77,7 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer( const TargetInstrInfo *TII = TM.getInstrInfo(); assert(TII && "No InstrInfo?"); - return new PPCHazardRecognizer970(*TII); + return new PPCHazardRecognizer970(TM); } return new PPCScoreboardHazardRecognizer(II, DAG); |
