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author | Hal Finkel <hfinkel@anl.gov> | 2013-04-10 18:30:16 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-10 18:30:16 +0000 |
commit | 30ae22914173e7c9f3c83b7d12c3dd50b3478ce7 (patch) | |
tree | 02106e2475566598faa8db6db85e46dfc5cd8936 /llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | |
parent | ea1d1a2d05700a8a7d92b139ab8e21664f90cafa (diff) | |
download | bcm5719-llvm-30ae22914173e7c9f3c83b7d12c3dd50b3478ce7.tar.gz bcm5719-llvm-30ae22914173e7c9f3c83b7d12c3dd50b3478ce7.zip |
PPC: Don't predicate a diamond with two counter decrements
I've not seen this happen in practice, and probably can't until we start
allowing decrement-counter-based conditional branches to be double predicated,
but just in case, don't allow predication of a diamond in which both sides have
ctr-defining branches. Even though the branching behavior of these can be
predicated, the counter-decrementing behavior cannot be.
llvm-svn: 179199
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 8abe5ff2e33..c9674575d75 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -876,6 +876,29 @@ bool PPCInstrInfo::FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, return true; } +static bool MBBDefinesCTR(MachineBasicBlock &MBB) { + for (MachineBasicBlock::iterator I = MBB.begin(), IE = MBB.end(); + I != IE; ++I) + if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8)) + return true; + return false; +} + +// We should make sure that, if we're going to predicate both sides of a +// condition (a diamond), that both sides don't define the counter register. We +// can predicate counter-decrement-based branches, but while that predicates +// the branching, it does not predicate the counter decrement. If we tried to +// merge the triangle into one predicated block, we'd decrement the counter +// twice. +bool PPCInstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, + unsigned NumT, unsigned ExtraT, + MachineBasicBlock &FMBB, + unsigned NumF, unsigned ExtraF, + const BranchProbability &Probability) const { + return !(MBBDefinesCTR(TMBB) && MBBDefinesCTR(FMBB)); +} + + bool PPCInstrInfo::isPredicated(const MachineInstr *MI) const { unsigned OpC = MI->getOpcode(); switch (OpC) { |