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author | Kit Barton <kbarton@ca.ibm.com> | 2016-02-26 21:11:55 +0000 |
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committer | Kit Barton <kbarton@ca.ibm.com> | 2016-02-26 21:11:55 +0000 |
commit | 93612ec5f2f7e68c68b0619792d60631bb02e968 (patch) | |
tree | 909cfa2032bad80d88e77e9dabee99b533e47918 /llvm/lib/Target/PowerPC/PPCInstrFormats.td | |
parent | e50f74474378e2179e05c770516292ed152ed8db (diff) | |
download | bcm5719-llvm-93612ec5f2f7e68c68b0619792d60631bb02e968.tar.gz bcm5719-llvm-93612ec5f2f7e68c68b0619792d60631bb02e968.zip |
Power9] Implement new vsx instructions: compare and conversion
This change implements the following vsx instructions:
Quad/Double-Precision Compare:
xscmpoqp xscmpuqp
xscmpexpdp xscmpexpqp
xscmpeqdp xscmpgedp xscmpgtdp xscmpnedp
xvcmpnedp(.) xvcmpnesp(.)
Quad-Precision Floating-Point Conversion
xscvqpdp(o) xscvdpqp
xscvqpsdz xscvqpswz xscvqpudz xscvqpuwz xscvsdqp xscvudqp
xscvdphp xscvhpdp xvcvhpsp xvcvsphp
xsrqpi xsrqpix xsrqpxp
28 instructions
Phabricator: http://reviews.llvm.org/D16709
llvm-svn: 262068
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrFormats.td')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 4e03ed27653..36392b1304c 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -747,6 +747,13 @@ class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = RC; } +// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO] +class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list<dag> pattern> + : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> { + let A = xo2; +} + // XX*-Form (VSX) class XX1Form<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> @@ -820,6 +827,22 @@ class XX2Form_2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = XT{5}; } +class XX2_RD6_XO5_RS6<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL, dag IOL, + string asmstr, InstrItinClass itin, list<dag> pattern> + : I<opcode, OOL, IOL, asmstr, itin> { + bits<6> XT; + bits<6> XB; + + let Pattern = pattern; + + let Inst{6-10} = XT{4-0}; + let Inst{11-15} = xo2; + let Inst{16-20} = XB{4-0}; + let Inst{21-29} = xo; + let Inst{30} = XB{5}; + let Inst{31} = XT{5}; +} + class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin, list<dag> pattern> : I<opcode, OOL, IOL, asmstr, itin> { |