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author | Hal Finkel <hfinkel@anl.gov> | 2014-08-23 23:21:04 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2014-08-23 23:21:04 +0000 |
commit | 584a70c820a543ad98288f3a184cae0c4f290bd0 (patch) | |
tree | b225e63a3d3756df036f0788e54b9de108fe62ab /llvm/lib/Target/PowerPC/PPCInstrFormats.td | |
parent | c4c5180fb408e0eb3be50a7990aab110fcb0889c (diff) | |
download | bcm5719-llvm-584a70c820a543ad98288f3a184cae0c4f290bd0.tar.gz bcm5719-llvm-584a70c820a543ad98288f3a184cae0c4f290bd0.zip |
[PowerPC] Add support for dcbtst and icbt (prefetch)
Adds code generation support for dcbtst (data cache prefetch for write) and
icbt (instruction cache prefetch for read - Book E cores only).
We still end up with a 'cannot select' error for the non-supported prefetch
intrinsic forms. This will be fixed in a later commit.
Fixes PR20692.
llvm-svn: 216339
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCInstrFormats.td')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrFormats.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td index 2da4257d9f7..aa6849744d2 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td +++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td @@ -478,6 +478,21 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, let Inst{31} = 0; } +class XForm_icbt<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, + InstrItinClass itin> + : I<opcode, OOL, IOL, asmstr, itin> { + bits<4> CT; + bits<5> RA; + bits<5> RB; + + let Inst{6} = 0; + let Inst{7-10} = CT; + let Inst{11-15} = RA; + let Inst{16-20} = RB; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + class XForm_sr<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, InstrItinClass itin> : I<opcode, OOL, IOL, asmstr, itin> { |