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| author | Craig Topper <craig.topper@intel.com> | 2017-10-31 06:01:04 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-10-31 06:01:04 +0000 |
| commit | beed653135ea69f58b2eb44a4a26ece40c808a09 (patch) | |
| tree | 58c4f03964b609579c71c6b5c5bdd71e6f9568a4 /llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp | |
| parent | 21e7b53490a8c01fe5931b643455065591b5f5ba (diff) | |
| download | bcm5719-llvm-beed653135ea69f58b2eb44a4a26ece40c808a09.tar.gz bcm5719-llvm-beed653135ea69f58b2eb44a4a26ece40c808a09.zip | |
[X86] Make AVX512_512_SET0 XMM16-31 lower to 128-bit XOR when AVX512VL is enabled. Use 128-bit VLX instruction when VLX is enabled.
Unfortunately, this weakens our ability to do domain fixing when AVX512DQ is not enabled, but it is consistent with our 256-bit behavior.
Maybe we should add custom handling to domain fixing to allow EVEX integer XOR/AND/OR/ANDN to switch to VEX encoded fp instructions if the high registers aren't being used?
llvm-svn: 316978
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp')
0 files changed, 0 insertions, 0 deletions
