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authorHal Finkel <hfinkel@anl.gov>2011-10-17 04:03:49 +0000
committerHal Finkel <hfinkel@anl.gov>2011-10-17 04:03:49 +0000
commit6fa5697af0a59f4ccff58f8c3bf217de762469cd (patch)
tree12cde81f76686056c024f43b412c4448ce1a1e6e /llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
parent3e8aa65bc259957966dde939d94b9d5cc60fdadd (diff)
downloadbcm5719-llvm-6fa5697af0a59f4ccff58f8c3bf217de762469cd.tar.gz
bcm5719-llvm-6fa5697af0a59f4ccff58f8c3bf217de762469cd.zip
Add PPC 440 scheduler and some associated tests
llvm-svn: 142170
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp13
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index cddc9d858ad..3197fc85d71 100644
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -22,6 +22,19 @@
using namespace llvm;
//===----------------------------------------------------------------------===//
+// PowerPC 440 Hazard Recognizer
+void PPCHazardRecognizer440::EmitInstruction(SUnit *SU) {
+ const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
+ if (!MCID) {
+ // This is a PPC pseudo-instruction.
+ // FIXME: Should something else be done?
+ return;
+ }
+
+ ScoreboardHazardRecognizer::EmitInstruction(SU);
+}
+
+//===----------------------------------------------------------------------===//
// PowerPC 970 Hazard Recognizer
//
// This models the dispatch group formation of the PPC970 processor. Dispatch
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