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| author | Eric Christopher <echristo@gmail.com> | 2014-04-29 00:16:46 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2014-04-29 00:16:46 +0000 |
| commit | 612bb69bf70a67780617421d2937b97f0e1357db (patch) | |
| tree | ed80dc3666a80d8aba54ecb2602cef7efd598c52 /llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | |
| parent | 40af450562a7326c5bd0a94af732a1165f316591 (diff) | |
| download | bcm5719-llvm-612bb69bf70a67780617421d2937b97f0e1357db.tar.gz bcm5719-llvm-612bb69bf70a67780617421d2937b97f0e1357db.zip | |
None of these targets actually define their own CFI_INSTRUCTION
opcode so there's no reason to use the target namespace for it
rather than TargetOpcode.
llvm-svn: 207475
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp index a18fc72bd7d..e2941568f1e 100644 --- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp @@ -563,13 +563,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { assert(NegFrameSize); unsigned CFIIndex = MMI.addFrameInst( MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)).addCFIIndex(CFIIndex); + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) + .addCFIIndex(CFIIndex); if (HasFP) { unsigned Reg = MRI->getDwarfRegNum(FPReg, true); CFIIndex = MMI.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, FPOffset)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -577,7 +578,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { unsigned Reg = MRI->getDwarfRegNum(BPReg, true); CFIIndex = MMI.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, BPOffset)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } @@ -585,7 +586,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { unsigned Reg = MRI->getDwarfRegNum(LRReg, true); CFIIndex = MMI.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, LROffset)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } } @@ -602,7 +603,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { unsigned CFIIndex = MMI.addFrameInst( MCCFIInstruction::createDefCfaRegister(nullptr, Reg)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } } @@ -630,7 +631,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); continue; } @@ -638,7 +639,7 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( nullptr, MRI->getDwarfRegNum(Reg, true), Offset)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::CFI_INSTRUCTION)) + BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } } |
