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authorHal Finkel <hfinkel@anl.gov>2013-03-21 21:37:52 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-21 21:37:52 +0000
commit756810fe361be9604fd3fee2b7cff55a30c92010 (patch)
tree0cc87bcc1be3830c1e679057f103e9ab69f2455b /llvm/lib/Target/PowerPC/PPCCallingConv.td
parent9db060485c777f4b50dc5f4968221c353678575c (diff)
downloadbcm5719-llvm-756810fe361be9604fd3fee2b7cff55a30c92010.tar.gz
bcm5719-llvm-756810fe361be9604fd3fee2b7cff55a30c92010.zip
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions __builtin_{setjmp/longjmp} functional on PPC platforms. The implementation strategy is similar to that on X86, with the exception that a branch-and-link variant is used to get the right jump address. Credit goes to Bill Schmidt for suggesting the use of the unconditional bcl form (instead of the regular bl instruction) to limit return-address-cache pollution. Benchmarking the speed at -O3 of: static jmp_buf env_sigill; void foo() { __builtin_longjmp(env_sigill,1); } main() { ... for (int i = 0; i < c; ++i) { if (__builtin_setjmp(env_sigill)) { goto done; } else { foo(); } done:; } ... } vs. the same code using the libc setjmp/longjmp functions on a P7 shows that this builtin implementation is ~4x faster with Altivec enabled and ~7.25x faster with Altivec disabled. This comparison is somewhat unfair because the libc version must also save/restore the VSX registers which we don't yet support. llvm-svn: 177666
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCCallingConv.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPCCallingConv.td5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCCallingConv.td b/llvm/lib/Target/PowerPC/PPCCallingConv.td
index caeb1796f7a..2a680661d36 100644
--- a/llvm/lib/Target/PowerPC/PPCCallingConv.td
+++ b/llvm/lib/Target/PowerPC/PPCCallingConv.td
@@ -136,3 +136,8 @@ def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAV
F27, F28, F29, F30, F31, CR2, CR3, CR4,
V20, V21, V22, V23, V24, V25, V26, V27,
V28, V29, V30, V31)>;
+
+def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+def CSR_NoRegs_Altivec : CalleeSavedRegs<(add (sequence "V%u", 0, 31), VRSAVE)>;
+
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