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author | Chris Lattner <sabre@nondot.org> | 2006-11-04 05:27:39 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-11-04 05:27:39 +0000 |
commit | 6be726048e854b1aa495333cb72d4f3a3ce40952 (patch) | |
tree | 2909cd8a9a138497eaa1e16a36078520b8343177 /llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | |
parent | ed07f23c52fa0506cd5ab34604eb6742ddc06de8 (diff) | |
download | bcm5719-llvm-6be726048e854b1aa495333cb72d4f3a3ce40952.tar.gz bcm5719-llvm-6be726048e854b1aa495333cb72d4f3a3ce40952.zip |
Go through all kinds of trouble to mark 'blr' as having a predicate operand
that takes a register and condition code. Print these pieces of BLR the
right way, even though it is currently set to 'always'.
Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.
llvm-svn: 31449
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp')
-rw-r--r-- | llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp index ee57cbaaba8..47056de2ab7 100644 --- a/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp +++ b/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp @@ -236,6 +236,9 @@ namespace { printOperand(MI, OpNo+1); } + void printPredicateOperand(const MachineInstr *MI, unsigned OpNo, + const char *Modifier); + virtual bool runOnMachineFunction(MachineFunction &F) = 0; virtual bool doFinalization(Module &M) = 0; }; @@ -363,6 +366,33 @@ bool PPCAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, return false; } +void PPCAsmPrinter::printPredicateOperand(const MachineInstr *MI, unsigned OpNo, + const char *Modifier) { + assert(Modifier && "Must specify 'cc' or 'reg' as predicate op modifier!"); + unsigned Code = MI->getOperand(OpNo).getImm(); + if (!strcmp(Modifier, "cc")) { + switch ((PPC::Predicate)Code) { + case PPC::PRED_ALWAYS: return; // Don't print anything for always. + case PPC::PRED_LT: O << "lt"; return; + case PPC::PRED_LE: O << "le"; return; + case PPC::PRED_EQ: O << "eq"; return; + case PPC::PRED_GE: O << "ge"; return; + case PPC::PRED_GT: O << "gt"; return; + case PPC::PRED_NE: O << "ne"; return; + case PPC::PRED_UN: O << "un"; return; + case PPC::PRED_NU: O << "nu"; return; + } + + } else { + assert(!strcmp(Modifier, "reg") && + "Need to specify 'cc' or 'reg' as predicate op modifier!"); + // Don't print the register for 'always'. + if (Code == PPC::PRED_ALWAYS) return; + printOperand(MI, OpNo+1); + } +} + + /// printMachineInstruction -- Print out a single PowerPC MI in Darwin syntax to /// the current output stream. /// |