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| author | Jim Laskey <jlaskey@mac.com> | 2005-08-12 23:38:02 +0000 |
|---|---|---|
| committer | Jim Laskey <jlaskey@mac.com> | 2005-08-12 23:38:02 +0000 |
| commit | a568700618283e290a4fb692797b4a1263eeb127 (patch) | |
| tree | 361235d7a5732f47f719f6f27459597155a98e8d /llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | |
| parent | f6a762ada12d1b33f76a3213f9f33af0dd0cf2ff (diff) | |
| download | bcm5719-llvm-a568700618283e290a4fb692797b4a1263eeb127.tar.gz bcm5719-llvm-a568700618283e290a4fb692797b4a1263eeb127.zip | |
1. This changes handles the cases of (~x)&y and x&(~y) yielding ANDC, and
(~x)|y and x|(~y) yielding ORC.
llvm-svn: 22771
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp | 27 |
1 files changed, 24 insertions, 3 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp index cef895b5d20..500333fb296 100644 --- a/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp +++ b/llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp @@ -1717,10 +1717,17 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; } } + if (isOprNot(N.getOperand(1))) { + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); + BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } if (isOprNot(N.getOperand(0))) { - Tmp1 = SelectExpr(N.getOperand(0).getOperand(0)); - Tmp2 = SelectExpr(N.getOperand(1)); - BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1); + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); + BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp1).addReg(Tmp2); RecordSuccess = false; return Result; } @@ -1737,6 +1744,20 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { return Result; if (SelectIntImmediateExpr(N, Result, PPC::ORIS, PPC::ORI)) return Result; + if (isOprNot(N.getOperand(1))) { + Tmp1 = SelectExpr(N.getOperand(0)); + Tmp2 = SelectExpr(N.getOperand(1).getOperand(0)); + BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } + if (isOprNot(N.getOperand(0))) { + Tmp1 = SelectExpr(N.getOperand(1)); + Tmp2 = SelectExpr(N.getOperand(0).getOperand(0)); + BuildMI(BB, PPC::ORC, 2, Result).addReg(Tmp1).addReg(Tmp2); + RecordSuccess = false; + return Result; + } // emit regular or Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); |
