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authorHal Finkel <hfinkel@anl.gov>2013-03-29 08:57:48 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-29 08:57:48 +0000
commitc20a08d25bc02de9ac2c4f85694e680d1b86c67f (patch)
treeff0363ee8929b308d6930e3be398bd2cde7da074 /llvm/lib/Target/PowerPC/PPC.td
parent703a9870a27ab77ee54d227c971ae71453af1070 (diff)
downloadbcm5719-llvm-c20a08d25bc02de9ac2c4f85694e680d1b86c67f.tar.gz
bcm5719-llvm-c20a08d25bc02de9ac2c4f85694e680d1b86c67f.zip
Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They implement the standard floating-point rounding operations (floor, trunc, etc.). One caveat: frin (round to nearest) does not implement "ties to even", and so is only enabled in fast-math mode. llvm-svn: 178337
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC.td')
-rw-r--r--llvm/lib/Target/PowerPC/PPC.td27
1 files changed, 15 insertions, 12 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 27f7157a28d..01cd55ee271 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -59,6 +59,8 @@ def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
"Enable the fsqrt instruction">;
def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
"Enable the stfiwx instruction">;
+def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
+ "Enable the fri[mnpz] instructions">;
def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
"Enable the isel instruction">;
def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
@@ -76,7 +78,6 @@ def FeatureQPX : SubtargetFeature<"qpx","HasQPX", "true",
// CMPB p6, p6x, p7 cmpb
// DFP p6, p6x, p7 decimal floating-point instructions
// FLT_CVT p7 fcfids, fcfidu, fcfidus, fcfiduz, fctiwuz
-// FPRND p5x, p6, p6x, p7 frim, frin, frip, friz
// FRE p5 through p7 fre (vs. fres, available since p3)
// FRSQRTES p5 through p7 frsqrtes (vs. frsqrte, available since p3)
// LFIWAX p6, p6x, p7 lfiwax
@@ -132,14 +133,14 @@ def : ProcessorModel<"e5500", PPCE5500Model,
FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
def : Processor<"a2", PPCA2Itineraries,
[DirectiveA2, FeatureBookE, FeatureMFOCRF,
- FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
- FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
- /*, Feature64BitRegs */]>;
+ FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
+ FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
+ Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"a2q", PPCA2Itineraries,
[DirectiveA2, FeatureBookE, FeatureMFOCRF,
- FeatureFSqrt, FeatureSTFIWX, FeatureISEL,
- FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
- /*, Feature64BitRegs */, FeatureQPX]>;
+ FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
+ FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
+ Feature64Bit /*, Feature64BitRegs */, FeatureQPX]>;
def : Processor<"pwr3", G5Itineraries,
[DirectivePwr3, FeatureAltivec, FeatureMFOCRF,
FeatureSTFIWX, Feature64Bit]>;
@@ -151,19 +152,21 @@ def : Processor<"pwr5", G5Itineraries,
FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
def : Processor<"pwr5x", G5Itineraries,
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
- FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
+ FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
+ Feature64Bit]>;
def : Processor<"pwr6", G5Itineraries,
[DirectivePwr6, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
- Feature64Bit /*, Feature64BitRegs */]>;
+ FeatureFPRND, Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"pwr6x", G5Itineraries,
[DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
- FeatureFSqrt, FeatureSTFIWX, Feature64Bit]>;
+ FeatureFSqrt, FeatureSTFIWX, FeatureFPRND,
+ Feature64Bit]>;
def : Processor<"pwr7", G5Itineraries,
[DirectivePwr7, FeatureAltivec,
FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
- FeatureISEL, FeaturePOPCNTD, FeatureLDBRX,
- Feature64Bit /*, Feature64BitRegs */]>;
+ FeatureFPRND, FeatureISEL, FeaturePOPCNTD,
+ FeatureLDBRX, Feature64Bit /*, Feature64BitRegs */]>;
def : Processor<"ppc", G3Itineraries, [Directive32]>;
def : Processor<"ppc64", G5Itineraries,
[Directive64, FeatureAltivec,
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