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authorHal Finkel <hfinkel@anl.gov>2013-05-20 16:08:17 +0000
committerHal Finkel <hfinkel@anl.gov>2013-05-20 16:08:17 +0000
commit8ca388414754e5025c0a8339f8d342b029084b69 (patch)
treed68b90049f55648b908f4e01dbe675261007d469 /llvm/lib/Target/PowerPC/PPC.h
parentb3ad90d52dcea8c108192b5183d4ec885d6c9a29 (diff)
downloadbcm5719-llvm-8ca388414754e5025c0a8339f8d342b029084b69.tar.gz
bcm5719-llvm-8ca388414754e5025c0a8339f8d342b029084b69.zip
Add a PPCCTRLoops verification pass
When asserts are enabled, this adds a verification pass for PPC counter-loop formation. Unfortunately, without sacrificing code quality, there is no better way of forming counter-based loops except at the (late) IR level. This means that we need to recognize, at the IR level, anything which might turn into a function call (or indirect branch). Because this is currently a finite set of things, and because SelectionDAG lowering is basic-block local, this can be done. Nevertheless, it is fragile, and failure results in a miscompile. This verification pass checks that all (reachable) counter-based branches are dominated by a loop mtctr instruction, and that no instructions in between clobber the counter register. If these conditions are not satisfied, then an ICE will be triggered. In short, this is to help us sleep better at night. llvm-svn: 182295
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPC.h')
-rw-r--r--llvm/lib/Target/PowerPC/PPC.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPC.h b/llvm/lib/Target/PowerPC/PPC.h
index 28b654cf08d..2e7961014b1 100644
--- a/llvm/lib/Target/PowerPC/PPC.h
+++ b/llvm/lib/Target/PowerPC/PPC.h
@@ -31,6 +31,9 @@ namespace llvm {
class MCInst;
FunctionPass *createPPCCTRLoops(PPCTargetMachine &TM);
+#ifndef NDEBUG
+ FunctionPass *createPPCCTRLoopsVerify();
+#endif
FunctionPass *createPPCEarlyReturnPass();
FunctionPass *createPPCBranchSelectionPass();
FunctionPass *createPPCISelDag(PPCTargetMachine &TM);
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