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author | Peter Collingbourne <peter@pcc.me.uk> | 2018-05-21 19:20:29 +0000 |
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committer | Peter Collingbourne <peter@pcc.me.uk> | 2018-05-21 19:20:29 +0000 |
commit | dcd7d6c33112db3618798c1c037460cac58d7f9a (patch) | |
tree | 21a52d71cf6ec2df9a9d299ca4d4559cd4891382 /llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | |
parent | a29fe579f48dd1600b21aadae7e90f64d643aef8 (diff) | |
download | bcm5719-llvm-dcd7d6c33112db3618798c1c037460cac58d7f9a.tar.gz bcm5719-llvm-dcd7d6c33112db3618798c1c037460cac58d7f9a.zip |
MC: Separate creating a generic object writer from creating a target object writer. NFCI.
With this we gain a little flexibility in how the generic object
writer is created.
Part of PR37466.
Differential Revision: https://reviews.llvm.org/D47045
llvm-svn: 332868
Diffstat (limited to 'llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h')
-rw-r--r-- | llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h index d47b9a6e452..316fd2ccf35 100644 --- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h +++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h @@ -27,7 +27,7 @@ class MCAsmBackend; class MCCodeEmitter; class MCContext; class MCInstrInfo; -class MCObjectWriter; +class MCObjectTargetWriter; class MCRegisterInfo; class MCSubtargetInfo; class MCTargetOptions; @@ -49,15 +49,11 @@ MCAsmBackend *createPPCAsmBackend(const Target &T, const MCSubtargetInfo &STI, const MCTargetOptions &Options); /// Construct an PPC ELF object writer. -std::unique_ptr<MCObjectWriter> createPPCELFObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit, - bool IsLittleEndian, - uint8_t OSABI); +std::unique_ptr<MCObjectTargetWriter> createPPCELFObjectWriter(bool Is64Bit, + uint8_t OSABI); /// Construct a PPC Mach-O object writer. -std::unique_ptr<MCObjectWriter> createPPCMachObjectWriter(raw_pwrite_stream &OS, - bool Is64Bit, - uint32_t CPUType, - uint32_t CPUSubtype); +std::unique_ptr<MCObjectTargetWriter> +createPPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); /// Returns true iff Val consists of one contiguous run of 1s with any number of /// 0s on either side. The 1s are allowed to wrap from LSB to MSB, so |