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| author | Guozhi Wei <carrot@google.com> | 2017-05-11 22:17:35 +0000 |
|---|---|---|
| committer | Guozhi Wei <carrot@google.com> | 2017-05-11 22:17:35 +0000 |
| commit | 22e7da9597a267165ee03cbabd31c1e4c13c5cb9 (patch) | |
| tree | 5e9c276b36bf1155394ead773501a7db7d205fd6 /llvm/lib/Target/PowerPC/Disassembler | |
| parent | 09e91ac6ab8a184d92100e3b1a1c4b6a0b8dc47a (diff) | |
| download | bcm5719-llvm-22e7da9597a267165ee03cbabd31c1e4c13c5cb9.tar.gz bcm5719-llvm-22e7da9597a267165ee03cbabd31c1e4c13c5cb9.zip | |
[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0
According to Power ISA V3.0 document, the first source operand of mtvsrdd is constant 0 if r0 is specified. So the corresponding register constraint should be g8rc_nox0.
This bug caused wrong output generated by 401.bzip2 when -mcpu=power9 and fdo are specified.
Differential Revision: https://reviews.llvm.org/D32880
llvm-svn: 302834
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler')
| -rw-r--r-- | llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp index 12ffbfdeacc..11d22377611 100644 --- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp +++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp @@ -204,6 +204,17 @@ static const unsigned G8Regs[] = { PPC::X28, PPC::X29, PPC::X30, PPC::X31 }; +static const unsigned G80Regs[] = { + PPC::ZERO8, PPC::X1, PPC::X2, PPC::X3, + PPC::X4, PPC::X5, PPC::X6, PPC::X7, + PPC::X8, PPC::X9, PPC::X10, PPC::X11, + PPC::X12, PPC::X13, PPC::X14, PPC::X15, + PPC::X16, PPC::X17, PPC::X18, PPC::X19, + PPC::X20, PPC::X21, PPC::X22, PPC::X23, + PPC::X24, PPC::X25, PPC::X26, PPC::X27, + PPC::X28, PPC::X29, PPC::X30, PPC::X31 +}; + static const unsigned QFRegs[] = { PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7, @@ -301,6 +312,12 @@ static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, return decodeRegisterClass(Inst, RegNo, G8Regs); } +static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, + uint64_t Address, + const void *Decoder) { + return decodeRegisterClass(Inst, RegNo, G80Regs); +} + #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass |
