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| author | Simon Atanasyan <simon@atanasyan.com> | 2018-08-31 15:57:17 +0000 |
|---|---|---|
| committer | Simon Atanasyan <simon@atanasyan.com> | 2018-08-31 15:57:17 +0000 |
| commit | 3785e84cf2cdafb7c7adb0aabe896795acaee6e4 (patch) | |
| tree | 17f8fdde51cc6d319e39b4b59b4fd66b275f7f4d /llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp | |
| parent | bf07a50a98b312c02e7c4c53c701884975d00147 (diff) | |
| download | bcm5719-llvm-3785e84cf2cdafb7c7adb0aabe896795acaee6e4.tar.gz bcm5719-llvm-3785e84cf2cdafb7c7adb0aabe896795acaee6e4.zip | |
[mips] Fix `mtc1` and `mfc1` definitions for microMIPS R6
The `mtc1` and `mfc1` definitions in the MipsInstrFPU.td have MMRel,
but do not have StdMMR6Rel tags. When these instructions are emitted
for microMIPS R6 targets, `Mips::MipsR62MicroMipsR6` nor
`Mips::Std2MicroMipsR6` cannot find correct op-codes and as a result the
backend uses mips32 variant of the instructions encoding.
The patch fixes this problem by adding the StdMMR6Rel tag and check
instructions encoding in the test case.
Differential revision: https://reviews.llvm.org/D51482
llvm-svn: 341221
Diffstat (limited to 'llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions

