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authorUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-09 10:00:34 +0000
committerUlrich Weigand <ulrich.weigand@de.ibm.com>2013-07-09 10:00:34 +0000
commit55daa77901d88579ddb901f44b4e0bc3ce5469cb (patch)
tree8f99b024973a771a7ac52cc47bdc5abaac9c7779 /llvm/lib/Target/PowerPC/AsmParser
parent8d2d79d05f93c5ed8b3eba750b076ea3471eb1f0 (diff)
downloadbcm5719-llvm-55daa77901d88579ddb901f44b4e0bc3ce5469cb.tar.gz
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[PowerPC] Support ".machine any"
The PowerPC assembler is supposed to provide a directive .machine that allows switching the supported CPU instruction set on the fly. Since we do not yet check CPU feature sets at all and always accept any available instruction, this is not really useful at this point. However, it makes sense to accept (and ignore) ".machine any" to avoid spuriously rejecting existing assembler files that use this. llvm-svn: 185924
Diffstat (limited to 'llvm/lib/Target/PowerPC/AsmParser')
-rw-r--r--llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp27
1 files changed, 27 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 32cf373dba8..ab29ee77963 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -196,6 +196,7 @@ class PPCAsmParser : public MCTargetAsmParser {
bool ParseDirectiveWord(unsigned Size, SMLoc L);
bool ParseDirectiveTC(unsigned Size, SMLoc L);
+ bool ParseDirectiveMachine(SMLoc L);
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
@@ -1182,6 +1183,8 @@ bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
return ParseDirectiveWord(8, DirectiveID.getLoc());
if (IDVal == ".tc")
return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
+ if (IDVal == ".machine")
+ return ParseDirectiveMachine(DirectiveID.getLoc());
return true;
}
@@ -1227,6 +1230,30 @@ bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
return ParseDirectiveWord(Size, L);
}
+/// ParseDirectiveMachine
+/// ::= .machine [ cpu | "push" | "pop" ]
+bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
+ if (getLexer().isNot(AsmToken::Identifier) &&
+ getLexer().isNot(AsmToken::String))
+ return Error(L, "unexpected token in directive");
+
+ StringRef CPU = Parser.getTok().getIdentifier();
+ Parser.Lex();
+
+ // FIXME: Right now, the parser always allows any available
+ // instruction, so the .machine directive is not useful.
+ // Implement ".machine any" (by doing nothing) for the benefit
+ // of existing assembler code. Likewise, we can then implement
+ // ".machine push" and ".machine pop" as no-op.
+ if (CPU != "any" && CPU != "push" && CPU != "pop")
+ return Error(L, "unrecognized machine type");
+
+ if (getLexer().isNot(AsmToken::EndOfStatement))
+ return Error(L, "unexpected token in directive");
+
+ return false;
+}
+
/// Force static initialization.
extern "C" void LLVMInitializePowerPCAsmParser() {
RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
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