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authorRanjeet Singh <Ranjeet.Singh@arm.com>2015-06-30 11:30:42 +0000
committerRanjeet Singh <Ranjeet.Singh@arm.com>2015-06-30 11:30:42 +0000
commit5b119091a130c2a09e9128b9e874efabb7c9c69f (patch)
treef948f236beaf848c46c2c5d410bcb04f020682cf /llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
parentf256184693d166f23eb2d0ed6379e9348909c7d2 (diff)
downloadbcm5719-llvm-5b119091a130c2a09e9128b9e874efabb7c9c69f.tar.gz
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There are a few places where subtarget features are still
represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 llvm-svn: 241058
Diffstat (limited to 'llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp4
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index a699a55d3cb..d6c0db67370 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -277,6 +277,7 @@ class PPCAsmParser : public MCTargetAsmParser {
bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands, MCStreamer &Out,
uint64_t &ErrorInfo,
+ FeatureBitset &ErrorMissingFeature,
bool MatchingInlineAsm) override;
void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
@@ -1197,10 +1198,11 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
OperandVector &Operands,
MCStreamer &Out, uint64_t &ErrorInfo,
+ FeatureBitset &ErrorMissingFeature,
bool MatchingInlineAsm) {
MCInst Inst;
- switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
+ switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, ErrorMissingFeature, MatchingInlineAsm)) {
case Match_Success:
// Post-process instructions (typically extended mnemonics)
ProcessInstruction(Inst, Operands);
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