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author | Justin Lebar <jlebar@google.com> | 2016-10-28 21:44:00 +0000 |
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committer | Justin Lebar <jlebar@google.com> | 2016-10-28 21:44:00 +0000 |
commit | f0a80ba385b7e24e9f1cdb2a06fc6c77d7ddc062 (patch) | |
tree | c136e45ab01eb1e17ee90ae5180bb5b966496cb7 /llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | |
parent | 0ede5fb1bbdd2b19f1209d8e164633d56bbc2d6a (diff) | |
download | bcm5719-llvm-f0a80ba385b7e24e9f1cdb2a06fc6c77d7ddc062.tar.gz bcm5719-llvm-f0a80ba385b7e24e9f1cdb2a06fc6c77d7ddc062.zip |
[NVPTX] Compute 'rem' using the result of 'div', if possible.
Summary:
In isel, transform
Num % Den
into
Num - (Num / Den) * Den
if the result of Num / Den is already available.
Reviewers: tra
Subscribers: hfinkel, llvm-commits, jholewinski
Differential Revision: https://reviews.llvm.org/D26090
llvm-svn: 285461
Diffstat (limited to 'llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp index 313c6a67048..2e4764feff1 100644 --- a/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -278,6 +278,8 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM, setTargetDAGCombine(ISD::MUL); setTargetDAGCombine(ISD::SHL); setTargetDAGCombine(ISD::SELECT); + setTargetDAGCombine(ISD::SREM); + setTargetDAGCombine(ISD::UREM); // Library functions. These default to Expand, but we have instructions // for them. @@ -4132,6 +4134,37 @@ static SDValue PerformSELECTCombine(SDNode *N, DCI.DAG.getConstant(IntrinsicId, DL, VT), LHS, RHS); } +static SDValue PerformREMCombine(SDNode *N, + TargetLowering::DAGCombinerInfo &DCI, + CodeGenOpt::Level OptLevel) { + assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM); + + // Don't do anything at less than -O2. + if (OptLevel < CodeGenOpt::Default) + return SDValue(); + + SelectionDAG &DAG = DCI.DAG; + SDLoc DL(N); + EVT VT = N->getValueType(0); + bool IsSigned = N->getOpcode() == ISD::SREM; + unsigned DivOpc = IsSigned ? ISD::SDIV : ISD::UDIV; + + const SDValue &Num = N->getOperand(0); + const SDValue &Den = N->getOperand(1); + + for (const SDNode *U : Num->uses()) { + if (U->getOpcode() == DivOpc && U->getOperand(0) == Num && + U->getOperand(1) == Den) { + // Num % Den -> Num - (Num / Den) * Den + return DAG.getNode(ISD::SUB, DL, VT, Num, + DAG.getNode(ISD::MUL, DL, VT, + DAG.getNode(DivOpc, DL, VT, Num, Den), + Den)); + } + } + return SDValue(); +} + enum OperandSignedness { Signed = 0, Unsigned, @@ -4313,6 +4346,9 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N, return PerformANDCombine(N, DCI); case ISD::SELECT: return PerformSELECTCombine(N, DCI); + case ISD::UREM: + case ISD::SREM: + return PerformREMCombine(N, DCI, OptLevel); } return SDValue(); } |