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author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-07-28 16:32:22 +0000 |
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committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-07-28 16:32:22 +0000 |
commit | 89217f8835ede9729f15698095fbf7264e8c16aa (patch) | |
tree | 6cf2319f72274abcf256235d6a302b9cc5bdf605 /llvm/lib/Target/Mips | |
parent | 655e0edfd701255e1894bd5fac6e8b3dde1ef4ad (diff) | |
download | bcm5719-llvm-89217f8835ede9729f15698095fbf7264e8c16aa.tar.gz bcm5719-llvm-89217f8835ede9729f15698095fbf7264e8c16aa.zip |
TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC
Differential Revision: https://reviews.llvm.org/D22925
llvm-svn: 276997
Diffstat (limited to 'llvm/lib/Target/Mips')
-rw-r--r-- | llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 16 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp | 4 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.cpp | 2 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsInstrInfo.h | 2 | ||||
-rw-r--r-- | llvm/lib/Target/Mips/MipsLongBranch.cpp | 2 |
5 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 1ea48e0439d..b25396fff4d 100644 --- a/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -801,7 +801,7 @@ void MipsConstantIslands::computeBlockSize(MachineBasicBlock *MBB) { BBI.Size = 0; for (const MachineInstr &MI : *MBB) - BBI.Size += TII->GetInstSizeInBytes(MI); + BBI.Size += TII->getInstSizeInBytes(MI); } /// getOffsetOf - Return the current offset of the specified machine instruction @@ -818,7 +818,7 @@ unsigned MipsConstantIslands::getOffsetOf(MachineInstr *MI) const { // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->getInstSizeInBytes(*I); } return Offset; } @@ -1297,9 +1297,9 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPUIndex = CPUserIndex+1; unsigned NumCPUsers = CPUsers.size(); //MachineInstr *LastIT = 0; - for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); + for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); Offset < BaseInsertOffset; - Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { + Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) { @@ -1622,7 +1622,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { splitBlockBeforeInstr(*MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->getInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BBInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -1644,14 +1644,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { .addMBB(NextBB); } Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); adjustBBOffsetsAfter(MBB); return true; diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index b5ba770df7b..ca2c36539e6 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -602,7 +602,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { // Get instruction with delay slot. MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && + if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && DSI->isCall()) { // If instruction in delay slot is 16b change opcode to // corresponding instruction with short delay slot. @@ -692,7 +692,7 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, bool InMicroMipsMode = STI.inMicroMipsMode(); const MipsInstrInfo *TII = STI.getInstrInfo(); unsigned Opcode = (*Slot).getOpcode(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && + if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 && (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || Opcode == Mips::PseudoReturn)) continue; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index de0ceaff2ca..91f107f4a1d 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -398,7 +398,7 @@ bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const { } /// Return the number of bytes of code the specified instruction may be. -unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { switch (MI.getOpcode()) { default: return MI.getDesc().getSize(); diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index 2e55012eec4..bb0b306b199 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -92,7 +92,7 @@ public: virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; /// Return the number of bytes of code the specified instruction may be. - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, diff --git a/llvm/lib/Target/Mips/MipsLongBranch.cpp b/llvm/lib/Target/Mips/MipsLongBranch.cpp index e721312390d..c745e3da222 100644 --- a/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -179,7 +179,7 @@ void MipsLongBranch::initMBBInfo() { // Compute size of MBB. for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin(); MI != MBB->instr_end(); ++MI) - MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI); + MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); // Search for MBB's branch instruction. ReverseIter End = MBB->rend(); |